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Today's designers
are continually challenged with designing and integrating complete
digital sub-systems onto a single programmable logic device (PLD). The
value of these devices include the ability to shorten development
cycles for electronic equipment manufactures and to help them get the
product(s) to market faster. eDE Alliance offers a full range of design
services to meet our customer's requirements, including
- Floor planning
and optimization
- Synthesis to
target technology
- Timing closure
and timing optimization
- Hardware/Software
co-verification
- FPGA prototyping
- Integration of
Hardware/Software interface
eDE Alliance
has the expertise in using the latest tools for quickly developing,
simulating, and testing FPGA designs. These tools include
- Altera
- Quartus II, MaxPlus II, Exemplar, ModelSim, Synplify, Cadence
- Xilinx
- Foundation, Synplify, FPGA Express, Exemplar, ModelSim, Cadence
eDE Alliance
has the experience designing with many of the latest FPGAs products
from the major vendors in the market, including
- Altera
- Stratix, Stratix GX, Cyclone, APEX II,
APEX 20K, Mercury, MAX 7000
- Xilinx
- Virtex II Pro, Virtex II, Spartan IIE,
CoolRunner-I
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eDE Alliance
employs a set of design guidelines to help improve device performance
and enhance simulation testing. The following are some key design
guidelines that we employ:
- FPGAs are
developed using either Verilog or VHDLMaximize the use of synchronous
logic design rules with synchronous resets to maximize performance
- External clocks
are re-generated with PLLs to reduce skew
- Do not use
gated clocks or combinatorial clocks
- State machines
are encoded to reduce complexity and maximize performance.
- Used data path
pipelining
- All synchronous
memories
eDE Alliance
has extensive experience in developing IP cores for customer designs.
We have experience both in developing core designs as well as
implementing vendor supplied cores designs. The cores that have been
developed by us include
- MD5 Message
Digest
- SHA-1 Message
Digest
- AES Data
Encryption Standard
- Single Data
Rate SDRAM Controller
- SPI-4
- SPI-2
- I2C
- Fragmentation
and Re-Assembly function for IBM switch fabric
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