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eDE Alliance
has experienced Signal Integrity (SI) Analysis personnel ready to
assist you in the design of complex high-speed electronic designs.
As PCB designs
become more complex, with higher clock speeds, higher device switching
speeds, and higher component densities, the need to analyze SI before
prototype development is crucial for system timing, signal integrity
and EMI / EMC concerns.
eDE Alliance signal integrity analysis is used to
validate your design, signal topology and signal termination choices by
applying digital and / or analog signal integrity stimulus. We can also
make design suggestions that will ensure correct propagation and
symmetry of high-speed signals between components through connectors.
Our analysis
consists of both pre-layout and post-layout analysis ensuring optimal
high-speed board layout and material selections.
Our
expertise includes:
Signal
Integrity Analysis for most types of board design including:
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Signal
Integrity Modeling, used for validating and ensuring correct signal
integrity parameters, identifying and correcting design mistakes and
ensuring correct layout parameters. These include:
- Overshoot/Undershoot
- Ringback
- Impedance
Matching
- Signal Timing
Requirements
- EMI/EMC Analysis
- Bus
Architecture and Topology Design
- Trace
Separation Requirements
- Trace Flight
Time Speeds
High speed
design I/O modeling examples, including but not limited to:
- PCI, PCI-X, PCI
Express
- SPI-3 and SPI-4
- Rapid I/O
- HyperTransport
- Utopia
- Processor Busses
- Memory
Interfaces
- Switch Fabric
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